The present invention relates to semiconductor memory devices and methods of fabrication. More particularly, the invention relates to semiconductor memory devices including a power decoupling capacitor and method of fabricating same.
Contemporary semiconductor memory devices are formed from a multiplicity of elements operatively arranged in various circuits. One common element regularly appearing in such circuits is the capacitor. Capacitors are commonly used in some types of memory devices to form memory cells capable of storing data. That is, a capacitor is used within each memory cell to store an amount of electrical charge indicative of a certain data value. For example, each memory cell in a dynamic random access memory (DRAM) includes a transistor and a capacitor. Charge is introduced or removed from the capacitor via the corresponding transistor to define a data state (i.e., a “1” or “0” data state for a single bit memory cell). Ideally, charge stored on a memory cell capacitor would be stably maintained for a long period of time. Accordingly, capacitors having relatively high capacitance are advantageous, since they better maintain charge over time.
Capacitors are used in many other circuits within semiconductor memory devices. In one type of circuit, a capacitor is used to dampen or cancel undesired signal reflections (or echoes) on a signal line. In another type of circuit, a capacitor is connected to a power terminal to buffer rapid fluctuation in a power supply voltage. That is, the capacitor acts as a low pass filter. When used in filter circuits, capacitors having a relatively high capacitance are advantageous since they better maintain charge.
The capacitance of a capacitor is highly correlated to its dielectric which is a material sandwiched between the two conductive surfaces (e.g., plates) forming the body of the capacitor. The capacitance of a capacitor is also proportional to the area of the conductive surfaces separated by the dielectric, and inversely proportional to a distance between the conductive surfaces. These physical relationships pose great challenges to circuit designers and fabrication specialists in the field of semiconductor memory devices, since shrinking device size reduces the size of most, if not all, constituent elements, including capacitors. Reduced capacitor size leads to a reduced surface area for its conductive surfaces, which leads to a reduction in the capacitance of the capacitor.